1. Field of the Invention
The present invention relates to a solid state image sensing device, and, more particularly, to a multi-output CCD solid state image sensing device.
2. Description of the Related Art
Today, the drive frequencies of horizontal CCD registers increase due to the increased resolution of solid state image sensing devices, which raises the problem of increased power consumption. One way of overcoming this problem is the use of the multi-output solid state image sensing device disclosed in Unexamined Japanese Patent Publication No. Hei 3-124176. To reduce the drive frequency, the image sensing area of this device is segmented into a plurality of partial image sensing areas and horizontal CCD registers and output sections are provided in association with the partial image sensing areas. This type of solid state image sensing device will now be discussed.
FIG. 1 is a block diagram of a conventional multi-output solid state image sensing device. This multi-output solid state image sensing device has an image sensing area where plural columns of pixels are arranged in parallel, each column of pixels consisting of a column of photoelectric conversion elements comprised of a plurality of photodiodes 1-1, and vertical CCD registers 1-3 coupled via transfer gates 1-2 to the associated photodiodes 1-1. The image sensing area is segmented to a plurality of partial image sensing areas 1a to 1d in the horizontal direction, in association with which horizontal CCD registers 2a to 2d are provided. Those horizontal CCD registers 2a-2d are respectively provided with output sections 3a to 3d.
Although the image sensing area of the illustrated device is divided to four partial image sensing areas, the number of segments is in no way limited to four. Strictly, several transfer stages of the image sensing area on the side of the horizontal CCD registers are covered with a light shielding film to be optical black areas. Although the illustrated case uses photodiodes as photoelectric conversion areas, the vertical CCD registers may also serve as photoelectric conversion areas.
In the multi-output solid state image sensing device, as the image sensing area is horizontally divided to four segments which are associated with four output sections, four output signals are acquired in parallel. Therefore, all the signals from the image sensing area can be output in one fourth the time needed to output all the signals from a single output section. In other words, with the use of four output sections, if the output time is the same, the signal output process may be accomplished in four times as long as the actually needed time. That is, the drive frequency of each of the horizontal CCD registers 2a-2d is reduced to 1/4, so that the consumed power of the horizontal CCD registers (which is proportional to the capacitance and the drive frequency) can be reduced to about 1/4.
The aforementioned Unexamined Japanese Patent Publication No. Hei 3-124176 does not describe a specific connecting structure for the horizontal CCD registers 2a-2d to the output sections 3a-3d. Let us consider the case where output sections based on a floating diffusion type charge sensor, the conventionally ordinary technology, (which are called "floating diffusion layer type amplifiers") are adapted to a multi-output solid state image sensing device.
FIG. 2A is a plan view showing the probable structure of the portion around the output section in the conventional multi-output solid state image sensing device. FIG. 2A shows the vicinity of the output section 3b. A plurality of vertical transfer electrodes (four vertical transfer electrodes per stage; only two of the vertical transfer electrodes, 12-3 and 12-4, at the last stage illustrated) are formed above the vertical CCD register channels 11a and 11b, and a device isolating layer (channel stopper) 13 is formed between the channels. Formed under the vertical transfer electrode 12-4 are horizontal CCD register channels 14a and 14b above which a plurality of horizontal transfer electrodes are formed. In the illustrated case, the horizontal transfer electrodes are driven by 2-phase pulses; the same pulse .phi.H.sub.1 or .phi.H.sub.2 is applied to a set of a storage electrode 15-2 and a barrier electrode 15-1. At one end of the horizontal CCD register 2b, the horizontal CCD register channel is bent in the opposite direction to the vertical CCD registers, and dummy horizontal transfer electrodes are formed on that channel. The dummy horizontal transfer electrodes, like the horizontal transfer electrodes, are driven by 2-phase pulses; the same pulse .phi.H.sub.1 or .phi.H.sub.2 is likewise applied to a set of a storage electrode 17-2 and a barrier electrode 17-1. There are several stages of dummy horizontal transfer electrodes. An output gate electrode 18, a floating diffusion layer 19, a reset gate electrode 20, a reset drain 21 and a source follower type amplifier 23 are provided adjacent to the last dummy transfer electrode. The floating diffusion layer 19 is connected to the gate electrode of a driver transistor at the first stage of the source follower type amplifier 23 by a wire 22, made of a conductive material like aluminum, tungsten or polysilicon. A device isolating layer is formed between the horizontal CCD register channels 14a and 14b.
The output operation will be discussed below. In the horizontal blanking period shown in FIG. 2B, signal charges stored in the channel under the vertical transfer electrode 12-3 are transferred to the horizontal CCD register channel (i.e., the channel under the horizontal transfer electrode to which the horizontal transfer pulse .phi.H.sub.1 is applied) via the channel under the vertical transfer electrode 12-4. In the horizontal effective period, signal charges are sequentially transferred toward the output sections in the horizontal direction. At the same time, the signal charges in the channel under the horizontal transfer electrodes 15b-1 and 15b-2 associated with the left end of the partial image sensing area 1b are transferred to the channel under the dummy horizontal transfer electrodes 17-1 and 17-2 (the transfer section is indicated by "T"). The signal charges which have been transferred to the channel under the last dummy horizontal transfer electrode are transferred to the floating diffusion layer 19, passing under the output gate electrode 18. Consequently, the potential of the floating diffusion layer 19 changes, and the changed potential is detected via the source follower type amplifier 23. When the reset gate electrode 20 is enabled after the detection of the signal charges, the potential of the floating diffusion layer 19 is reset to the potential of the reset drain 21.
While output sections based on a floating gate type charge sensor (called "floating gate type amplifiers") may be adapted to a multi-output solid state image sensing device, this scheme is not highly recommended because, as is well known, it suffers a lower charge sensitivity due to its detection capacitance being higher than that of the floating diffusion layer type amplifiers.
With the above structure, the channel length of the transfer section indicated by "T" in FIG. 2A, i.e., the transfer channel length at the time of transferring charges, which have reached the channel under the horizontal transfer electrode associated with the left end of one partial image sensing area, to the channel under the dummy horizontal transfer electrode, becomes equivalent to the lengthwise channel length under the horizontal transfer electrode or the channel width of the horizontal CCD register. While the horizontal transfer electrode normally has a length of about 1 to 3 .mu.m, the width of the horizontal CCD register channel is set to approximately 10 to 30 .mu.m, larger than the length of the horizontal transfer electrode. It is therefore very difficult to transfer charges, which have reached the channel under the horizontal transfer electrode associated with the left end of the partial image sensing area, to the dummy horizontal transfer electrode within the same time as needed for horizontal transfer, and the transfer efficiency becomes lower. Generally speaking, the individual horizontal CCD registers should be aligned on a line in order to set the transfer channel length similar to that of the horizontal transfer section. This design requires at least output gate electrodes and floating diffusion layers between the individual horizontal CCD registers. It is however apparent that the space for the provision of such elements cannot be secured.